Many electronics applications include communications channels that have transmitter and receiver components to move data through the electronics application, and the receiver components can include clock tracking features to recover a sampling clock from the received data. At-rate clock tracking circuits (e.g., a baud-rate clock data recovery (CDR) circuit, such as a “Muller-Mueller CDR”) can feedback data samples and error samples to recover clock timing information, such that the rate of the resulting clock signal is the data rate. Tracking the clock allows the receiver to sample a received data signal in the center of the “data eye,” thereby improving the accuracy of recovering data bit information from the data signal.
At-rate CDR techniques extract timing information by analyzing a channel pulse response at one or more sample locations and determining whether current clocking appears to be early or late with respect to the pulse response, then shifting the clocking signal (e.g., advancing or retarding the phase of the clocking signal), as appropriate. Such early/late determinations can be frustrated by various factors, such as clock jitter. For example, at-rate clock tracking circuits for high-speed serial links are typically implemented to handle two-level data encoding, such as “non-return-to-zero” (NRZ) encoding. With such an encoding scheme, early/late determinations (generally referred to herein as “CDR voting”) are based on attempting to recover data symbols in context of four types of transitions (e.g., +1 to +1, +1 to −1, −1 to −1, or −1 to +1), and jitter can cause errors in the CDR voting. For various reasons, it can be desirable to use higher-order encoding schemes that encode bits into more than two levels, such as “four-level pulse amplitude modulation” (PAM4) encoding. Higher-order encoding schemes can saddle a clock tracking circuit with more types of transitions to decode, which can cause the CDR voting to be appreciably more susceptible to jitter.